Reconfigurable Microelectronic Devices (architecture, development tools, programming language)

The course provides students with comprehensive introduction to

• FPGA architecture,
• FPGA design flow and tools
• Verilog Hardware Description Language
• FPGA programming and debugging.

Lectures and labs will be provided to introduce state-of-art tools and techniques needed to implement digital designs on FPGA platforms.

The course includes practical hands-on exercises with using FPGA development boards to implement, test, and debug your digital designs.

Students will gain theoretical knowledge and practical experience of:

• Using modern FPGAs for implementing digital designs
• Using Verilog HDL for coding digital designs
• Using Verilog HDL for coding testbenches
• Using a state-of-art tools for simulating, synthesizing, placing and routing, implementing and debugging digital designs

The cultural program includes:

• Boat city tour for students to get acquainted with the beauty of the city.
• Excursion to the Hermitage, one of the world’s largest and oldest museums of fine art.
• Visit to the “Baltika” Brewery/"Coca-Cola" factory where students can learn about the construction and logistic peculiarities of the plant.
• Picnic at the seashore of the Gulf of Finland where students can enjoy Russian style barbecue.
• Excursion to Pushkin, former tzar summer residence famous for its palace and park ensemble. Students will visit the outstanding Catherine Palace with glorious Amber room (optional, for extra price).
• Excursion to Peterhof  palace-ensemble with picturesque gardens, a countless number of fountains and giant golden statues (optional, for extra price).

- A basic understanding of digital circuits and sequential logic is required.

- Good command of English. All classes and extracurricular activities are carried out in English. Knowledge of the Russian language is not required.

- Applicants are expected to have at least 2 years of University level studies. 

4 ECTS

• Introduction to modern FPGAs architecture / lectures- 2 hours /
• Introduction to state-of-art design tools and FPGA based design flow / lectures – 8 hours; labs – 8 hours /
• Introduction to Verilog HDL for coding design / lectures – 12 hours; labs – 12 hours /
• Introduction to Verilog HDL for coding testbenches / lectures – 12 hours; labs – 12 hours /
• Introduction to timing analysis / lectures – 2 hours; labs – 2 hours /
• Introduction to design optimization / lectures – 2 hours; labs –2 hours / 
• Introduction to design implementation and debugging / lectures – 2 hours; labs – 4 hours /